1. Field of the Invention
This invention generally relates to a semiconductor circuit and particularly to a power supply switching circuit suitable for use in a device which requires a high supply voltage only during programming, such as an erasable programmable read only memory (EPROM) and an electrically erasable programmable read only memory (EEPROM).
2. Description of the Prior Art
In EPROMs and EEPROMs, a high voltage V.sub.pp of 20-21 V is typically required during programming as an internal supply voltage and a voltage V.sub.cc of typically 5 V is required as an internal supply voltage during read out operation. A V.sub.pp pin provided as one of the terminals of a packaged semiconductor device, such as an EPROM and EEPROM, was first used exclusively for application of V.sub.pp voltage to be used for programming and it was not used for application of a signal having other voltage levels. Moreover, the EPROM ordinarily had an N-channel MOS (Metal-Oxide-Semiconductor) structure and thus its internal power supply switching circuit was also constructed by N-channel MOS transistors. However, with an improvement in density and an increase of memory capacity, there has recently been developed an EPROM having a CMOS (Complementary MOS) structure so as to reduce the amount of power consumption. In order to prevent the number of pins from increasing due to such an increase in memory capacity, it has come to use the same single pin for the application of programming voltage V.sub.pp and mode control signal, which is called V.sub.pp /READ pin. During programming or write operation, high voltage V.sub.pp is applied to the V.sub.pp /READ pin; on the other hand, during read out operation, a mode control signal of 0-5 V is applied to this pin. With the adoption of CMOS structure, an internal power supply switching circuit must also be constructed in the form of CMOS structure.
FIG. 1 illustrates a prior art power supply switching circuit having a CMOS structure. As shown, the circuit includes an input terminal 11 to which a supply voltage of V.sub.cc is applied. The terminal 11 is connected to a drain electrode of N-channel enhancement transistor 20. The circuit includes another input terminal 12 for receiving another supply voltage of V.sub.pp. The terminal 12 is connected to a drain electrode of N-channel enhancement transistor 19. The source electrodes of transistors 19 and 20 are commonly connected to an output terminal 14. The circuit of FIG. 1 includes a further input terminal 13 to which a power supply switching control signal PRG is applied. This terminal 13 is connected to a gate electrode of transistor 20 which is thus turned on if PRG signal is high thereby causing the voltage level at the terminal 14 to be V.sub.cc '. On the other hand, the terminal 13 is also connected to a gate electrode of N-channel transistor 18 through a reverse current preventing transistor 15 and a CMOS inverter comprised of a pair of P-channel and N-channel transistors 17 and 18, and, thus, if PRG signal is low, the transistor 17 is turned on thereby causing the gate voltage of transistor 19 to be V.sub.pp, so that the transistor 19 is also turned on to set the voltage level at the terminal V.sub.pp to be V.sub.pp '.
The CMOS inverter is comprised by the transistors 17 and 18 which are series-connected, and the transistor 17 has its source electrode connected to the V.sub.pp supply voltage with the source electrode of transistor 18 connected to ground. The transistors 17 and 18 defining a CMOS inverter have their gate electrodes commonly connected to the source electrode of N-channel transistor 15 and also to the drain electrode of P-channel transistor 16. The transistor 16 has its source electrode connected to receive the V.sub.pp supply voltage and its gate electrode connected to the drain electrode of each of transistors 17 and 18. Thus, if PRG signal is high, the voltage at the gate electrode of each of the transistors 17 and 18 is set at V.sub.pp thereby causing the transistor 17 to be turned off and the transistor 18 to be turned on. That is, the voltage at the gate electrode of transistor 19 is set at 0 V to have the transistor 19 turned off.
The transistor 15 has its source electrode connected to the input terminal 13 and its gate electrode connected to receive the supply voltage V.sub.cc, and it serves to prevent a reverse current, corresponding to V.sub.cc level or more, from being supplied to the terminal 13. The above-described circuit is typically constructed on a P-conductivity type substrate, which is to be connected to ground while operation, using the well-known CMOS process. Thus, the voltage at the substrate of N-channel transistors 15, 18, 19 and 20 is at ground level. On the other hand, the P-channel transistors 16 and 17 are formed in an N-well and the substrate voltage of these transistors 16 and 17 is set at V.sub.pp by having the source electrode connected to the substrate in each of these transistors 16 and 17.
In the circuit of FIG. 1, output voltages at the output terminal 14 may be switched by controlling the conditions of transistors 19 and 20 depending on the state of PRG signal. However, the output voltage from each of the transistors 20 and 19 becomes reduced from V.sub.cc and V.sub.pp by the amount of threshold voltage drop. That is, if PRG signal is high, the voltages at the gate and drain electrodes of transistor 20 are both at V.sub.cc and its source voltage V.sub.cc ' as an output voltage becomes V.sub.cc '=V.sub.cc -V.sub.T1, where V.sub.T1 is a threshold voltage of transistor 20. On the other hand, if PRG signal is low, the gate and drain voltages of transistor 19 are both at V.sub.pp so that its source voltage V.sub.pp ' as an output voltage becomes V.sub.pp '=V.sub.pp -V.sub.T2, where V.sub.T2 is a threshold voltage of transistor 19. Furthermore, since the substrates of transistors 19 and 20 are connected to ground, the threshold voltages V.sub.T1 and V.sub.T2 of these transistors contain the so-called body effect components V.sub.T1 and V.sub.T2. Since these body effect components increase more as the output voltage becomes higher, so that the effects of voltage drop, in particular, at the transistor 19 which carries out switching of high voltage V.sub.pp cannot be neglected.
FIG. 2 shows another prior art circuit directed to prevent the occurrence of a voltage drop in output voltage as described above. As shown, the circuit of FIG. 2 is constructed by substituting the transistor 19 of FIG. 1 with a P-channel transistor 19' whose source electrode is connected to the substrate and to the input terminal 12 and whose drain electrode is connected to the output terminal 14 with the gate electrode connected to the drain electrode of transistor 17. The circuit of FIG. 2 includes an input terminal 13' to which PRG signal is applied. In such a structure, it is true that a voltage drop may be prevented from occurring; however, if 0 V is applied to the terminal 12 as a mode control signal with the PRG signal being low ( during read out operation ), a forward bias is established between the drain electrode and the N-well substrate of P-channel transistor 19' because the voltage at the drain electrode of transistor 19' becomes V.sub.cc even though the source electrode and N-well susbtrate of transistor 19' are set at 0 V, so that there appears a problem of current flow toward the terminal 12.